ID:15065 Clock input port inclk[<number>] of PLL "<name>" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block

CAUSE: The specified input port of the specified PLL is driven by an illegal source. The clock input port of a PLL must be driven by a non-inverted input pin or by a clock output of another PLL, optionally through a Clock Control Blocks instead of dedicated routing.

ACTION: Modify the design so that the clock input port of the specified PLL is driven by a non-inverted input pin or another PLL.