ID:11577 The <name> node's ARESET/ACLR port is illegally connected. All registers in an IOREG must use the same ARESET signal.

CAUSE: Your design has instantiated an I/O hardware configuration that is either illegal or not currently supported by Quartus Prime. DDIO_OUTs, FFs, and OUTPUT_ALIGNMENTs in the same IO_REG must share the same source for their ARESET inputs.

ACTION: Modify the connectivity of this node so that the node has a legal configuration.