ID:14164 Can't remap output clock port clk[<number>] of PLL "<name>" for target device family because PLLs in target device can have only output clock ports clk[<number>] to clk[<number>]

CAUSE: The specified PLL was created for a device family that is different from the target device family and that uses the specified clk port. Analysis & Synthesis cannot remap the clk port in the PLL to a clk port in a PLL for the target device family because the target device can have only the specified range of clk ports.

ACTION: Modify the PLL to use only the clk ports available to PLLs in the target device family.