ID:177027 PLL can drive only <max number of extclks> external clock signals, but this PLL drives <number driving>: <name>

CAUSE: The specified phase-locked loop (PLL) is trying to drive more I/O pins than the device can provide.

ACTION: Drive fewer I/O pins from this PLL or change the type of I/O pins. Differential and pseudo-differential I/O pins require more connections from the PLL.