ID:177034 Row clock network in the region bounded by (<top left X>,<top left Y>) and (<bottom right X>,<bottom right Y>) is <overused or congested>

CAUSE: The Fitter encountered congestion in this row clock network while trying to connect the clock driver to its fan-outs. Clock routing from global sources has limited routing to logic array blocks (LABs) in this region and your design may try to exceed that limit.

ACTION: Use the Chip Planner to view the congested region and driving cells. Remove clock driver location constraints, if needed, to allow the Fitter to try different locations in different regions. Otherwise, reduce the clock network usage in your design, either by using fewer clocks, or by using smaller clocks instead of larger ones. For example, you can use regional clocks instead of global clocks.