ID:19889 Could not find valid LAB location to facilitate routing of core global signal "<name>" near chip coordinates (<x>, <y>).

CAUSE: In Intel FPGA architectures with programmable clock routing (like Stratix 10), promoted signals that originate from core logic require a LAB resource in order to connect to the programmable clock grid. In this compilation, the Fitter was not able to find any free LAB resources to make this connection.

ACTION: Ensure there is at least one available LAB location near the target position where the promoted signal will enter the programmable clock grid. LAB locations covered by reserved Logic Lock regions (for a different entity than the promoted core signal) or that contain location-constrained or preserved logic, would not be considered available.