Security Page (Device and Pin Options Dialog Box)

You open this page by clicking Assignments > Device > Device and Pin Options > Security.

Allows you to specify options for managing power, such as the bus speed mode and the address of the voltage regulator when in PMBus Master mode.

Table 1. Assembler Security Settings. For Stratix^® 10 devices, specifies settings for programming bitstream authentication, encryption, scrambling, and other eFuse enabled security options. To access these settings, click Assignments > Device > Device and Pin Options > Security. Disabled options are unavailable for the current device or configuration mode.
Option	Description
Quartus Key File	Specifies the first level signature chain file (.qky) that you generate. This chain includes the root key (.pem) and one or more design signing keys (.pem) required to sign the bitstream and allow access to the FPGA when using authentication or encryption.
Encryption key storage select	Specifies the location that stores the .qek key file. You can select either Battery Backup RAM or eFuses for storage.
Encryption update ratio	Specifies the ratio of configuration bits compared to the number of key updates required for bitstream decryption. You can select either 31:1 (the key must change 1 time every 31 bits) or Disabled (no update required). Encryption supports up to 20 intermediate keys.
Enable scrambling	Scrambles the configuration bitstream.
More Options	Opens the More Security Options dialog box for specifying additional physical security options.