Dual Simplex (DS) Assignment Editor (Assignments Menu)

For designs with supported HSSI IP targeting Agilex™ 5 FPGAs only, you can create and view dual simplex logical assignments according to your planned bank and channel arrangement. After defining dual simplex groups in the DS Assignment Editor, you run the HSSI Dual Simplex IP Generation stage of the Compiler to generate the dual simplex IP for synthesis. To use DS Assignment Editor to assign DS groups and run HSSI Dual Simplex IP Generation, follow these steps:
  1. Open a Quartus® Prime Pro Edition project that targets the Agilex™ 5 device and includes a Platform Designer system that contains HSSI IP that support dual simplex mode.
  2. In Compilation Dashboard, click the IP Generation substep. The Messages window reports when generation is complete.
  3. Click Assignments > Dual Simplex (DS) Assignment Editor. The DS Assignment Editor lists all supported dual simplex IP in your design in the IP List and any previously created dual simplex assignments under DS Groups.
  4. Create dual simplex groups and assign IP instances in DS Assignment Editor:
    • Right-click any instance under IP List and click Create instance in > New DS group.
    • Double-click the Name cell under DS Groups and type a new group name.
    • Right-click the DS Groups row and select Create DS Group.
    • Double-click any DS Group name to specify a unique DS group name that becomes the module name for the Verilog output.
  5. To place instances in a DS group, right-click the instance name and click Move to group. The visualizer shows the assigned channels and indicates any illegal assignments.
  6. Under Loopback Mode, double-click in the cell to optionally enable an available loopback mode for debug. NO_LOOPBACK is the default setting.
  7. For any IP instance, double-click the Name cell to optionally specify a new instance name for the IP, and a Relative Offset from the origin location in units of channels.
  8. To specify shared clock properties for any assigned IP instance, select the instance under DS Groups, turn on Shared Clock, and specify IP Port and Merge Port
  9. View the DS assignments in the visualizer display of the Current Group. The visualizer and the Message panel indicate any illegal assignments. The visualizer display shows two rectangles that represent the simplex IP in two channels. These rectangles represent the Tx and Rx channels, respectively. You can select the Current Group that you want to visualize. Illegal assignments appear with red hashmarks in the rectangle, and an error message displays in the Message panel.
  10. When your DS assignments are complete, click the Save Assignments button to save the DS assignments to the .qsf for application during subsequent compilation stages.
  11. In the Compilation Dashboard, click HSSI Dual Simplex IP Generation to generate the dual simplex IP.
Note: For details on configuring dual simplex IP, refer to the GTS Transceiver PHY User Guide.