Testbench System

  • Create testbench Platform Designer system—Creates a new testbench system that includes Avalon® Verification Suite bus functional models (BMFs) for the exported interfaces. After generating this testbench system, you can open it in Platform Designer to view or modify the BFMs.
  • Create testbench simulation model—Allows you to generate a simulation model in Verilog or VHDL at the same time as the testbench system. Use this option if you want to use the Platform Designer-generated testbench system directly. If you want to make changes to the Platform Designer-generated system, open the testbench system in Platform Designer to make the changes and then generate a simulation model for that system.
  • Allow mixed-language simulation—Allows a mixed language testbench simulation model generation. If turned on, if a preferred simulation language is set, Platform Designer uses a fileset of the component for the simulation model generation. When turned off, which is the default, Platform Designer uses the selected language for the simulation model.