Synthesis Files

Allows you to manage the files that are created when an instance of the component generates the Intel® Quartus® Prime synthesis model. You can specify the following attributes for each file in the table:

  • Output Path—The name of the generated file, which can be different than the input file name.
  • Source File—The path to the original file that is copied to the output path during generation.
  • Type—The type of file. If a file is an HDL file that can be synthesized, or one of the supported file types, you should specify a matching file type. You can include extra files as generated output that are not synthesized as part of the Intel® Quartus® Prime design; you must specify the file type for these extra files as OTHER.
  • Attributes—You can specify a single synthesis file as the top-level file, which contains the top-level module.

The following options are available in the Synthesis Files table:

  • + (Add)—Allows you to add a file to the list of synthesis files.
  • - (Remove)— Allows you to remove the selected file from the list of synthesis files.
  • Analyze Synthesis Files— Analyzes the HDL files to discover information about the modules defined in the top-level file. When analysis is complete, you can then select the top-level module. Once the top-level file is selected, Platform Designer updates the parameters and signals for the component to match those found in the top-level module.
  • Create Synthesis File from Signals—If there are no files in the synthesis files list, you can define your signals and interfaces and use the Create Synthesis File from Signals feature to create a synthesis HDL file based on the signals in the component.
  • Top-level Module—Specifies the module in the top-level file that defines the interface for the component.