Board-level Signal Integrity Analysis Settings
Allows you to select HSPICE to generate HSPICE Simulation Deck File (.sp) Definition or IBIS to generate IBIS Output File (.ibs) Definition.
The following settings are available for generation of custom IBIS models using the EDA Netlist Writer GUI:
| Setting | Description |
|---|---|
| Format | Specifies IBIS as the format for output generation of custom IBIS models for board level signal integrity analysis in supported third-party tools. |
| IBIS version | Specifies the IBIS version 5.0 or 4.2 for the custom IBIS model you generate. Only version 5.0 is available for Agilex™ FPGA portfolio devices. |
| Output directory | Specifies the directory path for custom IBIS model generation. By default, the path is <project>/board/ibis. |
| Enable model selector | Enables the model selector feature that lists all the possible models for each I/O cell in the design. This setting is turned off by default. |
| Enable extended model selector | Enables the extended model selector feature. This setting is an extension of the Enable model selector setting. The extension lists additional models for I/O standards with Class I and II. This setting is turned off by default. |
| Enable per pin RLC package model with mutual coupling | Allows you to generate the per pin RLC package model with mutual coupling. The lumped RLC package model information appears in the IBIS output file. This setting is turned off by default except for Agilex™ FPGA portfolio devices. |
| Enable IBIS-AMI (GPIO Only) | Enables generation of IBIS-AMI models that you can use to model high-speed serial and parallel links that include transmitter and receiver equalization algorithms. This setting is available for only Agilex™ 5 devices and Agilex™ 7 M-Series devices. This setting is turned off by default for all applicable devices. |