Device-Independent Models

Logical Library Model File Compile For Notes
altera altera_primitives.vhd Quartus® Prime primitives  
altera_primitives_components.vhd Quartus® Prime primitives  
altera_ver altera_primitives.v Intel FPGA IP cores  
altera_mf altera_mf.vhd Intel FPGA IP cores For VHDL-93 compliant designs
altera_mf_components.vhd Intel FPGA IP cores  
altera_mf_ver altera_mf.v Intel FPGA IP cores  
lpm 220model.vhd Intel FPGA IP library of parameterized modules  
220pack.vhd Intel FPGA IP library of parameterized modules  
lpm_ver 220model.v Intel FPGA IP library of parameterized modules  
altera_lnsim altera_lnsim.sv Required for Stratix® V and later devices. SystemVerilog file used for VHDL and Verilog HDL simulation
altera_lnsim_components.vhd Required for Stratix® V and later devices  
altera_lnsim_ver altera_lnsim.sv (all but Mentor) family-independent models SystemVerilog file used for VHDL and Verilog HDL simulation
\mentor\altera_lnsim_for_vhdl.v family-independent models  
sgate sgate_pack.vhd Libraries of high-level primitives  
sgate.vhd Libraries of high-level primitives  
sgate_ver sgate.v Libraries of high-level primitives