To perform a gate-levelfunctional simulation with the QuestaSim GUI

  1. If you have not already done so, set up a project with the QuestaSim software.
  2. To map the design libraries to your work library:
    1. On the File menu, point to New and click Library. The Create a New Library dialog box appears.
    2. Type lpm in the Library Name box, type the name of the work library in the Library Maps to box, and then click OK.
    3. Repeat steps 2a and 2b to map altera_mf to the work library.
  3. To compile the functional simulation libraries, Verilog HDL or VHDL Design Files, and testbench files (if you are using a testbench):
    1. On the Compile menu, click Compile.
    2. In the Library list of the Compile HDL Source Files dialog box, select the work library.
    3. In the File name list, type the directory path and file name of the appropriate simulation libraries.

      In the Files of Type list, select All Files (*.*), and in the Look in list select the Verilog HDL or VHDL Design File.

    4. Click Compile.
      Note: For VHDL designs that use the 220model.vhd library, turn on Use Explicit Declarations under Default Options in the Compile dialog box.
    5. Repeat steps 3b to 3d to compile the Verilog HDL or VHDL Design File.
    6. Repeat steps 3b to 3d to compile the testbench file(s).
    7. Click Done.
  4. To load the design:
    1. On the Simulate menu, click Simulate. The Simulate dialog box appears.
    2. In the Name list, click the + icon to expand the work directory.
    3. Select the top-level design file to simulate.
    4. Click Add.
    5. Click Load.
  5. Perform the functional simulation in the QuestaSim software.