Running Gate-Level Functional Simulation from the Command-Line

To use the Questa^® - Intel^® FPGA Edition software, provided with the Quartus^® Prime software, to perform a gate-level functional simulation of a VHDL or Verilog HDL design that contains Intel-specific components using command-line commands:

If you have not already done so, set up a Questa^® - Intel^® FPGA Edition project with command-line commands.
To compile the Verilog HDL or VHDL Design Files and testbench files (if you are using a testbench), type the following commands at the prompt.
For VHDL designs:
```
vcom -work work <design name> .vhd
vcom -work work <testbench> .vhd
```
For Verilog HDL designs:
```
vlog -work work <design name> .v
vlog -work work <testbench> .v
```
To load the design, type the following commands at the prompt.
For VHDL designs: vsim work.
<top-level design entity>
For Verilog HDL designs:
vsim -L altera_mf_ver -L lpm_ver <top-level design module>
Perform the gate-level functional simulation in the Questa^® - Intel^® FPGA Edition software.