Running Gate-Level Functional Simulation with the Questa® - Intel® FPGA Edition GUI

  1. If you have not already done so, set up a project with the Questa® - Intel® FPGA Edition software.
  2. To compile the Verilog HDL or VHDL Design Files and testbench files (if you are using a testbench):
    1. On the Compile menu, click Compile.
    2. In the Library list of the Compile Source Files dialog box, select the work library.
    3. In the File name list, type the directory path and file name of the .v file or .vhd file.

      In the Files of Type list, select All Files (*.*), and in the Look in list select the .v file or .vhd file.


      In the More EDA Netlist Writer Settings dialog box you can specify settings for generating functional simulation netlist files. If you have a VHDL Output File (.vho) Definition or Verilog Output File (.vo) Definition for use in a functional simulation, you should compile it before proceeding.

    4. Click Compile.
    5. Repeat steps 2b to 2d to compile the testbench file(s).
    6. Click Done.
  3. To load the design:
    1. On the Simulate menu, click Simulate.
    2. If you are simulating a Verilog HDL design, to specify the Questa® - Intel® FPGA Edition precompiled libraries:
      1. Click the Libraries tab.
      2. In the Search Libraries (-L) box, click Add and select the appropriate libraries.
      3. Click OK.
    3. In the Name list, click the + icon to expand the work directory.
    4. Select the top-level design file to simulate.
    5. Click Add.
    6. Click Load.
  4. Perform the functional simulation in the Questa® - Intel® FPGA Edition software.