Force PLL Output Counter logic option

A logic option that forces the counter the Compiler uses for a particular PLL clock output. By default, the Compiler automatically determines the best counter to use based on clock usage and other routing conflicts, however, setting this option forces the Compiler to use the counter you specify. Setting this option can cause clock routing problems, as the clock router cannot rotate counters to resolve conflicts.

Setting this option directs the Compiler to override the Preserve PLL Counter Order logic option assignment on a specified PLL.

Scripting Information

Keyword: pll_force_output_counter

Settings: C0 | C1 | C2 | C3 | C4 | C5 | C6 | C7 | C8 | C9