PLL PFD Clock Frequency logic option

This logic option specifies the phase frequency detector (PFD) clock frequency of the PLL. PLLs in Intel FPGAs align the rising edge of the reference input clock to a feedback clock using the PFD. The falling edges are determined by the duty-cycle specified by the user.

This option is available for the Stratix® V device family only.

Scripting Information

Keyword: pll_pfd_clock_frequency

Settings: <frequency>