Fast Output Enable Register logic option

A logic option that implements an output enable register in an I/O cell with a fast, direct connection to an I/O pin. Turning on the Fast Output Enable Register option can help maximize I/O timing performance, for example, by permitting fast clock-to-output enable times. Turning this option off for a particular signal prevents the Fitter from implementing the signal automatically in an I/O cell.

This option must be assigned to either a register or an output or bidirectional pin that has a tri- state buffer controlled by a register or it is ignored.