Extract VHDL State Machines logic option

Allows the Compiler to extract state machines from a VHDL Design File (.vhd) Definition . The Compiler optimizes state machines using special techniques to reduce area or improve performance. If this option is turned off, the Compiler extracts and optimizes state machines in VHDL Design Files as regular logic.

This option is useful for preventing automatic state machine optimizations to manually optimized logic.

Scripting Information

Keyword: extract_vhdl_state_machines

Settings: on* | off