Input Delay from Dual-Purpose Clock Pin to Fan-out Destinations logic option
Specifies the propagation delay from a dual-purpose clock pin to its fan-out destinations that are routed on the global clock network. Legal integer values range from 0 through 63, where 0 is the setting with the least delay and 63 is the setting with the most delay. Use this advanced option after you compile a project, check the I/O timing, and determine that the timing is unsatisfactory. For detailed information on how to use this option, refer to the data sheet for the device family.
This option is ignored if it is applied to anything other than an input or bidirectional pin, or if the pin is user-assigned to a non-dual-purpose clock pin location.
Scripting Information |
Keyword: dual_purpose_clock_pin_delay Settings: <integer> Legal integer values are 0 - 63 |