Netlist Optimizations logic option
This option is useful for preserving I/O timing on specific pins and registers in a design where you want to perform netlist optimization. This option is also useful for preserving the synthesis of a specific node or entity, for example, preserving the name of a register.
This option is ignored for gate-level retiming if it is applied to anything other than a register or a design entity containing registers. For synthesis and fitting, this option is ignored if it is applied to anything other than a logic cell or design entity.
Scripting Information |
Keyword: adv_netlist_opt_allowed Settings: "never allow" | "always allow" | default* *default |