max_depth Verilog HDL Synthesis Attribute

A Verilog HDL synthesis attribute that specifies the maximum depth of the TriMatrix memory blocks used to implement an inferred RAM Definition or ROM Definition in your design. You can use this attribute to force the software to implement a single deep RAM with several shallow TriMatrix memory blocks.

To use the max_depth synthesis attribute, apply the attribute to the declaration of a variable that represents a RAM or ROM in your design file.

// Limit the depth of the memory blocks implement "ram" to 512 // This forces the software to use two M512 blocks instead of one M4K block to implement this RAM

(* max_depth = 512 *) reg [7:0] ram[0:1023];