romstyle VHDL Synthesis Attribute

A VHDL synthesis attribute that specifies the type of TriMatrix Memory block to use when implementing an inferred ROM Definition in your design. This synthesis attribute is supported only for device families that support the TriMatrix Memory architecture.

Note: Analysis & Synthesis also recognizes the synonymous synthesis attribute syn_romstyle. This synthesis attribute behaves identically to the romstyle synthesis attribute.

To use the romstyle synthesis attribute, first declare the synthesis attribute with a string type. Then associate the romstyle synthesis attribute with a Signal or Variable Declaration that represents an inferred ROM with an attribute specification. Specify the synthesis attribute value as "logic", "M4K", "M9K", "M144K", or "MLAB", depending on the type of memory block that you want the Intel® Quartus® Prime software to use when you implement the inferred ROM. If you associate the synthesis attribute with any other VHDL object, or if you specify an illegal value, the Intel® Quartus® Primesoftware ignores that synthesis attribute.

For example, in the following code, the Attribute Declaration declares the romstyle synthesis attribute, and the Attribute Specification specifies that you use an M9K memory block Definitionto infer the RAM my_ram:

signal q : std_logic_vector(7 downto 0);


attribute romstyle : string;
attribute romstyle of q : signal is “M9K”;


rom_proc : process (clk) is
   if(rising_edge(clk)) then
       case A is
          when "00000" => q <= X"00";
          when "00001" => q <= X"01";
          when "00010" => q <= X"02";
          when "00011" => q <= X"03";
          when "00100" => q <= X"04";
          when "00110" => q <= X"05";
          when "00111" => q <= X"06";
          when "01000" => q <= X"07";
          when "01001" => q <= X"08";
          when "01010" => q <= X"09";

        end case;
   end if;
end process;