max_depth VHDL Synthesis Attribute

A VHDL synthesis attribute that specifies the maximum depth of the TriMatrix memory blocks used to implement an inferred RAM Definition or ROM Definition in your design. You can use this attribute to force the software to implement a single deep RAM or ROM with several shallow TriMatrix memory blocks.

To use the max_depth synthesis attribute, first declare the attribute with an integer type using an attribute declaration. Then use an attribute specification to associate the attribute with a signal or variable that represents a RAM or ROM in your design file.

-- Limit the depth of the memory blocks implementing "ram" to 512 -- This forces the software to use two M512 blocks instead of one M4K block to implement this RAM

attribute max_depth : integer; attribute max_depth of ram : signal is 512;