library VHDL Synthesis Directive

A VHDL synthesis directive that sets the destination library for the design units in a VHDL Design File (.vhd) Definition. This directive takes a single string argument: The name of the destination library. To use the library directive, embed it in a VHDL comment prior to the context clause for a primary design unit (a package, an entity, or a configuration), using one of the supported keywords for synthesis directives, i.e. synthesis, pragma, sysopsys, or exemplar.

The library directive overrides the default destination library work, the Library setting specified for the current file through the GUI, QSF or Tcl, and any prior library directive in the current file. The directive remains effective until the end of the file or the next library synthesis directive.

Note: For more information on specifying the destination library for VHDL design units, refer to Organizing a VHDL Design into Libraries.

In the following example, the library synthesis directive instructs Intel® Quartus® Prime to set the destination library to my_lib, creating it if necessary. Any design units that follow the directive, including the entity my_entity, will be added to my_lib.

-- synthesis library my_lib
library ieee;
use ieee.std_logic_1164.all;
entity my_entity(...)
end entity my_entity;