altera_attribute VHDL Synthesis Attribute

A VHDL synthesis attribute for making assignments in the Quartus® Prime software to objects in your HDL source files. You can the attribute to embed assignments in your source files when the assignments do not have a specific VHDL synthesis attribute. The attribute takes a single string value with the same syntax as an assignment in a Tcl script or the Quartus Prime Settings File (.qsf) Definition. The Quartus® Prime software only supports the altera_attribute on entities, instances, ports, and registers. If you apply the attribute to any other object, the synthesis ignores the attribute.

Note: Assignments made with the Quartus® Prime user interface, Tcl scripts and commands, and the Quartus Prime Settings File (.qsf) Definition, override assignments made with the altera_attribute, unless assignments made with the altera_attribute are more specific. More specific assignments override less specific assignments. For example, an entity assignment overrides a global assignment, and an instance assignment overrides an entity assignment.

Assignments made with the altera_attribute synthesis attribute are not displayed in the Assignment Editor or written to the Quartus Prime Settings File (.qsf) Definition. Assignments made with the altera_attribute synthesis attribute are listed in the Source Assignments report in the Analysis & Synthesis folder of the Compilation Report.

To use the altera_attribute synthesis attribute in a VHDL Design File (.vhd) Definition, declare the synthesis attribute using an Attribute Declaration, and then associate the altera_attribute synthesis attribute with a VHDL object using an Attribute Specification. The value of the altera_attribute attribute that you associate with the object must be a single string argument containing a list of .qsf assignments separated by semicolons (;), as shown in the following example:

attribute altera_attribute : string;
attribute altera_attribute of <object> : <entity class> is "<assignment>[;<assignment>..]";

Where each <assignment> has the form of:

-name <name> <value> [-to <target>] [-from <source>] [-section_id section]

In this string argument:

  • <name> is the name of the .qsf variable.
  • <value> is the .qsf variable's corresponding value.
  • <target> is the optional tag that specifies the target instance to which the assignment applies within this entity.
  • <source> is the optional tag that specifies the source instance to which the assignment applies within this entity.
  • <section> is the optional tag that specifies the section to which the assignment applies.

For example, to set the .qsf assignment SYNCHRONIZER_IDENTIFICATION FORCED on a sync_reg register, specify the following:

attribute altera_attribute : string;
attribute altera_attribute of sync_reg : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED";

You can optionally divide the assignment into multiple lines by using the following format:

attribute altera_attribute : string;
attribute altera_attribute of <object> : <entity class> is 
"-name <name_1> <value_1> [-to <target_1>] [-from <source_1>] [-section_id section_1];" & 
"-name <name_2> <value_2> [-to <target_2>] [-from <source_2>] [-section_id section_2]";

Not all assignment types require a target, a source, or a section. If a .qsf variable requires a string value, use nested quotes around the value, as the following example shows:

attribute altera_attribute of reg1: signal is
     "-name VARIABLE_NAME ""STRING_VALUE""";
Note: To find the .qsf variable name that corresponds to an option or assignment, specify a value for the option or assignment using the Quartus® Prime user interface, and note the changes that occur in the .qsf.

The following example shows how to use the altera_attribute synthesis attribute to set the power-up level of an inferred register:

signal my_reg : std_logic attribute;
attribute altera_attribute : string;
attribute altera_attribute of my_reg : signal is "-name POWER_UP_LEVEL HIGH";

process (clk)
begin
      if (rising_edge(clk)) then
            my_reg <= d;
      end if;
end process;

The following example shows how to use the altera_attribute synthesis attribute to specify a synthesis logic option for an entity. In this example, the synthesis attribute turns off the Auto Shift Register Recognition logic option. You can associate the attribute with an entity or an architecture for the entity. This example shows an altera_attribute associated with an architecture:

entity my_entity is
-- Declare ports and generics
end my_entity;

architecture rtl of my_entity is
     attribute altera_attribute : string;
     attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
begin
     -- specify the architecture body
end rtl;

The following example shows how you can also use altera_attribute for more complex assignments involving more than one instance. In this example, the following VHDL sample uses an altera_attribute to cut all timing paths from q1 to q2:

signal q1, q2 : std_logic;
attribute altera_attribute : string;
-- equiv to set_instance_assignment -name CUT ON -from q1 -to q2
attribute altera_attribute of q1 : signal is "-name CUT ON -to q2";

You may specify either the -to option or the -from option in a single altera_attribute. Synthesis automatically sets the remaining option to the target of the altera_attribute. You may also specify wildcard characters Definition for either option. For example, if you specify * for the -to option instead of q2, the Quartus® Prime software cuts all timing paths from q1 to every other register in the design.