WIRE (Block Design Files only) Primitive


Output Description:

Input Description:


OUT = input


The WIRE primitive is used to rename a node or bus line. WIRE primitives do not have any associated logic behavior.

The WIRE primitive is directional; that is, on a bidirectional bus, you can use only one WIRE primitive to rename the input or output portion of the bus.

Note: In Verilog HDL, the buf gate primitive has the same functionality as the WIRE primitive. For information about Quartus® Prime primitive instantiation, go to Using a Quartus® Prime Logic Function.