Parameter Type Required Description

Specifies whether the JTAG I/O selection is enabled. If enabled, a select input port is used and drives a mux that selects the JTAG I/O between the interface on this Intel® FPGA IP and the interface on the JTAG hard controller. As mux is added on tck, a clock input to registers, clock skew may occur. You are responsible for timing closure, and no extra fitter support is provided for it. A non-zero value enables this parameter; zero disables it. The default is 0.