sld_signaltap IP Core

The sld_signaltap IP allows you to instantiate Signal Tap Logic Analyzer instances in your design earlier in the design cycle when using the Signal Tap Logic Analyzer and without the need for a Signal Tap File (.stp) Definition. Designs containing Signal Tap Logic Analyzer IP instances can be compiled without a Signal Tap File. The sld_signaltap IP is available for all Intel device families supported by the Quartus® Prime software except the MAX® series.

To create a Signal Tap File from Signal Tap Logic Analyzer IP instances, on the File menu, point to Create/Update and click Create Signal Tap File from Design Instance(s).

Intel recommends instantiating this function with the IP Catalog.


When you create your IP instance, you can use the IP Catalog to generate a netlist for third-party synthesis tools.

Note: For more information about using the sld_signaltap IP with the IP Catalog, refer to the Design Debugging Using the Signal Tap Embedded Logic Analyzer.