Input Ports

data[]

No

Data input to the shift register.

Input port LPM_WIDTH wide. At least one of the data, aset, aclr, sset, sclr and/or shiftin ports must be used.

clock

Yes

Positive-edge-triggered clock.

enable

No

Clock enable input.

The shift options also use the enable input for the clock enable. For serial operation, enable must be high (1). For parallel load operation, load must be high (1) and enable must be high or unconnected.

shiftin

No

Serial shift data input.

At least one of the data, aset, aclr, sset, sclr and/or shiftin ports must be used. The default value is VCC.

load

No

Synchronous parallel load. High (1) equals load operation, and low (0) equals shift operation.

Default is low (0) shift operation. For parallel load operation, load must be high (1), and enable must be high or unconnected.

sclr

No

Synchronous clear input.

Clears the q[] outputs. If both the sset and sclr ports are used and asserted, the value of the sclr port is used.

sset

No

Synchronous set input.

Sets the q[] outputs to the value specified by LPM_SVALUE, if that value is present, or sets the q outputs to all 1s. If both sset and sclr are used and both are asserted, sclr is used.

aclr

No

Asynchronous clear input.

Asynchronously clears the q[] outputs. If both aset and aclr are used and both are asserted, aclr is used.

aset

No

Asynchronous set input.

Sets q[] outputs to the value specified by LPM_AVALUE, if that value is present, or sets the q[] outputs to all 1s. If both aset and aclr are used and both are asserted, aclr is used.