Input Ports
Port Name |
Required |
Description |
Comments |
|---|---|---|---|
address[] |
Yes |
Address input to the memory. |
Input port LPM_WIDTHAD wide. |
inclock |
No |
Clock for input registers. |
The address[] port is synchronous (registered) when the inclock port is connected, and is asynchronous (unregistered) when the inclock port is not connected. |
outclock |
No |
Clock for output registers. |
The addressed memory content-to-q[] response is synchronous when the outclock port is connected, and is asynchronous when it is not connected. |
memenab |
No |
Memory enable input. |
High is equal to data output on q[], and Low is equal to high-impedance outputs. This port is available for backward compatibility only and Altera recommends that you not use this port. |