lpm_ram_dq Intel® FPGA IP

Parameterized RAM with separate input and output ports Intel® FPGA IP. Intel recommends usinglpm_ram_dq toimplement asynchronous memory or memory with synchronous inputs and/or outputs. This Intel® FPGA IP is provided only for backward compatibility; instead, Intel recommends using the altsyncram Intel® FPGA IP. The lpm_ram_dq function uses DFFE primitives or latch arrays in MAX3000 and MAX7000 devices, or if the USE_EAB parameter is set to "OFF". Intel strongly recommends using synchronous rather than asynchronous RAM functions.

  • The Compiler automatically implements this function in logic cells in MAX3000 and MAX7000 devices.
  • You can use the lpm_ram_dq Intel® FPGA IP to read data from and write data to in-system memory in devices with the In-System Memory Content Editor . To use the lpm_ram_dq Intel® FPGA IP with the In-System Memory Content Editor, you must turn on the Allow In-System Memory Content Editor to capture and update content independently of the system clock option (that is, the ENABLE_RUNTIME_MOD and INSTANCE_NAME parameters must be enabled) when instantiating the lpm_ram_dq Intel® FPGA IP with the IP Catalog.
  • You can use the Assignment Editor to add, change, or delete assignments and assignment values for Intel® FPGA IP.
Note: More information is available on the lpm_ram_dq Intel® FPGA IP on the Altera website.