Input Ports

Port Name	Required	Description	Comments
`arclk`	Yes	Clock for the address register.	The `arclk` port is used without an interface protocol only.
arclkena	No	Clock enable signal for the `arclk` clock.	Altera recommends changing the clock enable signal at the rising edge of the `arclk` clock. The clock enable takes place 1 clock cycle after the port value is changed.
`ardin`	Yes	Input for the address register.	The `ardin` port is used without an interface protocol only.
`arshft`	Yes	Shift signal for the address register.	The `arshft` port is used without an interface protocol only.
`drclk`	Yes	Clock for the data register.	The `drclk` port is used without an interface protocol only.
drclkena	No	Clock enable signal for the `drclk` clock.	Altera recommends changing the clock enable signal at the rising edge of the `drclk` clock. The clock enable takes place 1 clock cycle after the port value is changed.
`drdin`	Yes	Input for the data register.	The `drdin` port is used without an interface protocol only.
`drshft`	Yes	Shift signal for the data register.	The `drshft` port is used without an interface protocol only.
`erase`	Yes	Signal that controls the erase sequence.	The `erase` port is used without an interface protocol only.
`oscena`	No	Signal that enables the internal oscillator.	The `oscena` port is used without an interface protocol only. If the `osc` port is specified, the `oscena` port is required.
`program`	No	Signal that initiates a program sequence.	The `oscena` port is used without an interface protocol only.