Input Ports

Port Name

Required

Description

Comments

wren_a

No

Write enable input.

The wren_a port is not available when the OPERATION_MODE parameter is set to "ROM" mode.

rden_a

No

Read enable input port.

This port is available for Stratix® III devices only.

wren_b

No

Write enable input.

The wren_b input port is available only when the OPERATION_MODE parameter is set to "BIDIR_DUAL_PORT".

rden_b

No

Read enable input port.

The rden_b input port is available only when the OPERATION_MODE parameter is set to "DUAL_PORT" and when the RAM_BLOCK_TYPE parameter is not set to "M-RAM".

data_a[]

No

Data input port to the memory for port A.

Input port [WIDTH_A - 1..0] wide.

data_b[]

No

Data input port to the memory for port B.

Input port [WIDTH_B - 1..0] wide.

address_a[]

Yes

Address input to the memory for port A.

Input port [WIDTHAD_A - 1..0] wide.

address_b[]

Yes

Address input to the memory for port B.

Input port [WIDTHAD_B - 1..0] wide.

clock0

Yes

Clock input port for the RAM.

 

clock1

No

Clock input port for the RAM.

 

clocken0

No

Clock enable for clock0.

 

clocken1

No

Clock enable for clock1.

 

aclr0

No

The first asynchronous clear input.

 

aclr1

No

The second asynchronous clear input.

 

byteena_a[]

No

Byte enable input port.

Input port WIDTH_BYTEENA_A-1..0 wide. The byteena_a enable input port can be used only when the data_a port is at least 2 bytes wide.

byteena_b[]

No

Byte enable input port.

Input port WIDTH_BYTEENA_B-1..0 wide. The byteena_b enable input port can be used only when the data_b port is at least 2 bytes wide.