altstratixii_oct Intel® FPGA IP

Parameterized on-chip termination (OCT) Definition Intel® FPGA IP. The altstratixii_oct Intel® FPGA IP allows you to use the OCT block in user mode. In non-user mode, when you set pins to have calibrated termination, the OCT block configures once during initialization and then powers off. In user mode, the OCT block stays powered on and you can send an enable signal to tell the OCT block to recalibrate during runtime. User mode allows the termination control to adapt to changing conditions, such as variances in temperature or voltage.

User mode requires a clock signal and an enable signal from the design. Non-user mode requires no extra signals from the design. If you use the OCT block in user mode, you should use the altstratixii_oct Intel® FPGA IP. If you are not recalibrating the OCT block during runtime, you should use the OCT in non-user mode.

Note: The altstratixii_oct Intel® FPGA IP cannot be instantiated with the IP Catalog.