External double data rate (DDR) Definition memory PHY interface Intel® FPGA IP.

The ALTMEMPHY Intel® FPGA IP allows you to rapidly create highly configurable PHY, which safely transfer data between memory and user logic. You can use either a user-designed controller, or the Altera DDR, DDR2, and DDR3 SDRAM high-performance controllers with the ALTMEMPHY Intel® FPGA IP.

Note: When you create your Intel® FPGA IP, you can use the IP Catalog to generate a netlist for third-party synthesis tools. More information is available on the ALTMEMPHY Intel® FPGA IP on the Altera website