Input Ports
Port Name |
Required |
Description |
Comments |
|---|---|---|---|
clock |
Yes |
Write clock for RAM. Read clock for ROM. |
|
clken |
No |
Clock enable input port. |
Values are 0 (disabled) and 1 (enabled). If omitted, the default value is 1. |
init |
Yes |
Initialization from ROM enable. |
When asserted high, the init signal directs the Intel® FPGA IP to begin initializing from ROM. |
datain[] |
No |
Data input from external ROM. |
Input port [(width-1)..0] wide. This port is applicable in the external ROM mode only. |
rom_data_ready |
No |
Input port for external-ROM mode. |
When the PORT_ROM_DATA_READY parameter value is set to "PORT_USED", the rom_data_ready port is used in the external ROM mode. Assert this signal for each word of data when the altmem_init Intel® FPGA IP is ready to read the data. |