altdq_dqs Intel® FPGA IP

Parameterized data strobe Intel® FPGA IP. The altdq_dqs Intel® FPGA IP transmits and receives data on both edges of the reference clock. The altdq_dqs Intel® FPGA IP enables you to generate input-only, output-only, or bidirectional configuration variations. The altd_dqs Intel® FPGA IP is available for supported device (Stratix® IV and Stratix® V) families.

Note:
  • For this Intel® FPGA IP, the IP Catalog generates output files with multiple entities or modules. The top-level entity or module is located at the bottom of the file.
  • To interface with thepandn-pins, you can instantiate your altdq_dqs Intel® FPGA IP then instantiate anI/O buffer Intel® FPGA IP.
Note: More information is available on the altdq_dqs Intel® FPGA IP on the Altera website.