altdll Intel® FPGA IP

delay-locked loop (DLL) Definition Intel® FPGA IP. The altdll Intel® FPGA IP configures the DLL offset control. The altdll Intel® FPGA IP is available for the Arria® II GX, Stratix® III, Stratix® IV, and Stratix® V device families.

  • For this Intel® FPGA IP, the IP Catalog generates output files with multiple entities or modules. The top-level entity or module is located at the bottom of the file.
  • When you create your Intel® FPGA IP, you can use the IP Catalog to generate a netlist for third-party synthesis tools.
Note: More information is available on the altdll Intel® FPGA IP on the Altera website.