Parameters

Parameters Type Required Comments
PROTOCOL String Yes

Specifies the protocol. Values are "BASIC", "CEI", "CPRI", "SRIO", "SDI_HD", "SDI_3G", "HT_3_0", "HT_1_0", "SONET_OC96", "SONET_OC48", "SONET_OC12", "PCIE", "PCIE2", "XAUI", "GIGE", "BIST", and "PRBS".
NUMBER_OF_CHANNELS Integer Yes

Specifies the number of GXB receiver or transmitter channels. Values are [1..32].
OPERATION_MODE String Yes

Specifies the operation of the altgx Intel® FPGA IP. Values are "RX", receiver mode, "TX", transmitter mode, and "DUPLEX", receiver and transmitter mode. If omitted, the default is "DUPLEX".
LOOPBACK_MODE String Yes

Specifies the operation of the loopback. Values are "NONE", "SLB", "PLB","POSTCDR_RSLB", and"RPLB".

If omitted, the default is"NONE". A value of"POSTCDR_RSLB"or"RPLB"is available only when theOPERATION_MODEparameter is set to"DUPLEX".

Value

Description

"NONE"

There is no loopback mode.

"SLB"

Enables the serial loopback mode.

"PLB"

Enables the parallel loopback mode.

"POSTCDR_RSLB"

Enables the reverse serial loopback mode.

"RPLB"

Enables the reverse parallel loopback mode.
STARTING_CHANNEL_NUMBER Integer Yes

Specifies the index number for the first channel in the GXB. Value must be in multiples of four beginning with 0.
RECEIVER_TERMINATION String No

Specifies the receiver data input pin termination value. Values are "OCT_100_OHMS", "OCT_120_OHMS", "OCT_150_OHMS", and "OFF". If omitted, the default is"OFF".
TRANSMITTER_TERMINATION String No

Specifies the transmitter termination value. Values are "OCT_100_OHMS", "OCT_120_OHMS", "OCT_150_OHMS", and "OFF". If omitted, the default is "OFF".
RX_CHANNEL_WIDTH Integer Yes

Specifies the width of the dataout signal from the GXB receiver channel atom into the programmable logic device (PLD) source. Values are [8,10,16,20,32,40].
TX_CHANNEL_WIDTH Integer Yes

Specifies the width of the dataout signal from the GXB transmitter channel atom into the PLD source. Values are [8,10,16,20,32,40].
RX_DIGITALRESET_PORT_WIDTH Integer No

Specifies the width of the receiver reset input signals rx_digitalreset and rx_analogreset. The value can be set to either number_of_channels or the number of bonded units.
TX_DIGITALRESET_PORT_WIDTH Integer No

Specifies the width of the transmitter reset input signal tx_digitalreset. The value can be set to either number_of_channels or the number of bonded units.
RECONFIG_DPRIO_MODE Integer No

Specifies the required reconfiguration type. Values are [1,2].

Value Description

1

When set to 1, the internal CRAM bits for the channel change due to reconfiguration.

2

When set to 2, the interface to the PLD changes due to reconfiguration.
RECONFIG_PROTOCOL String No Specifies the reconfiguration protocol. Values are "XAUI", "GIGE", "PIPE", "SONET", "3G_BASIC", "3G_BASIC", "6G_BASIC", and "CPRI". If omitted, the default is "BASIC".
RX_USE_DOUBLE_DATA_MODE String No

Specifies whether to use double data width mode. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE". If the value is set to "TRUE", the value of RX_CHANNEL_WIDTH must be 16, 20, 32, or 40.
TX_USE_DOUBLE_DATA_MODE String No

Specifies whether byte serializer is used. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".

RX_CRU_INCLOCK0_PERIOD

 String No

Specifies the input clock signal period for theclock recovery unit (CRU) Definition Values are "TRUE" and "FALSE". This parameter indicates the input clock period for the rx_cruclk input port when the RX_USE_CRUCLK parameter is set to "TRUE".

RX_CRU_INCLOCK1_PERIOD

 Integer No

Specifies the input clock signal period, in picoseconds (ps), for the index1 clock source of the CRU. This parameter is available only when the RECONFIG_DPRIO_MODE parameter value is set to CMU PLL reconfiguration. This parameter is used for reconfiguration.

RX_CRU_INCLOCK2_PERIOD

 Integer No

Specifies the input clock signal period, in picoseconds (ps), for the index2 clock source of the CRU. This parameter is available only when the RECONFIG_DPRIO_MODE parameter value is set to CMU PLL reconfiguration. This parameter is used for reconfiguration.

RX_CRU_INCLOCK3_PERIOD

 Integer No

Specifies the input clock signal period, in picoseconds (ps), for the index3 clock source of the CRU. This parameter is available only when the RECONFIG_DPRIO_MODE parameter value is set to CMU PLL reconfiguration. This parameter is used for reconfiguration.

RX_CRU_INCLOCK4_PERIOD

 Integer No

Specifies the input clock signal period, in picoseconds (ps), for the index4 clock source of the CRU. This parameter is available only when the RECONFIG_DPRIO_MODE parameter value is set to CMU PLL reconfiguration. This parameter is used for reconfiguration.

RX_CRU_INCLOCK5_PERIOD

 Integer No

Specifies the input clock signal period, in picoseconds (ps), for the index5 clock source of the CRU. This parameter is available only when the RECONFIG_DPRIO_MODE parameter value is set to CMU PLL reconfiguration. This parameter is used for reconfiguration.

RX_CRU_INCLOCK6_PERIOD

 Integer No

Specifies the input clock signal period, in picoseconds (ps), for the index6 clock source of the CRU. This parameter is available only when the RECONFIG_DPRIO_MODE parameter value is set to CMU PLL reconfiguration. This parameter is used for reconfiguration.
RX_CRU_INCLOCK7_PERIOD Integer No

Specifies the input clock signal period, in picoseconds (ps), for the index7 clock source of the CRU. This parameter is available only when the RECONFIG_DPRIO_MODE parameter value is set to CMU PLL reconfiguration. This parameter is used for reconfiguration.
RX_CRU_INCLOCK8_PERIOD Integer No

Specifies the input clock signal period, in picoseconds (ps), for the index8 clock source of the CRU. This parameter is available only when the RECONFIG_DPRIO_MODE parameter value is set to CMU PLL reconfiguration. This parameter is used for reconfiguration.
RX_CRU_INCLOCK9_PERIOD Integer No

Specifies the input clock signal period, in picoseconds (ps), for the index9 clock source of the CRU. This parameter is available only when the RECONFIG_DPRIO_MODE parameter value is set to CMU PLL reconfiguration. This parameter is used for reconfiguration.
TX_RECONFIG_DATA_RATE Integer No Specifies the rate of data out from the transmitter after DPRIO reconfiguration in Mbps.
TX_RECONFIG_DATA_RATE_REMAINDER Integer No

Specifies the remainder of the DATA_RATE parameter in bps during reconfiguration.
RX_DPRIO_MODE String No

Specifies the DPRIO mode. Values are "NONE", "PMA_ELECTRICALS", and "FULL". If omitted, the default is "NONE". When set to "NONE", the DPRIO is not used by the receiver. When set to "PMA_ELECTRICALS", the DPRIO is used by the receiver. When set to "FULL", the DPRIO is used by the receiver with full programmability.
TX_DPRIO_MODE String No

Specifies the DPRIO mode. Values are "NONE", "PMA_ELECTRICALS", and "FULL". If omitted, the default is "NONE". When set to "NONE", the DPRIO is not used by the transmitter. When set to "PMA_ELECTRICALS", the DPRIO is used by the transmitter. When set to "FULL", the DPRIO is used by the transmitter with full programmability.
RX_RECONFIG_CLK_SCHEME String No

Specifies the clocking scheme for reconfiguration in the receiver. Values are "INDV_CLK_SOURCE", "TX_CH0_CLK_TO_RX", and "TX_CLK_TO_RX". If omitted, the default is "TX_CLK_TO_RX". When set to "INDV_CLK_SOURCE", all receivers are clocked using their individual clock source. When set to "TX_CH0_CLK_TO_RX", all receivers are clocked by a single transmitter clock source. When set to "TX_CLK_TO_RX", all receivers are clocked by their respective channel transmitter clock source.
TX_RECONFIG_CLK_SCHEME String No

Specifies the clocking scheme for reconfiguration in the transmitter. Values are "INDV_CLK_SOURCE" and "TX_CH0_CLK_SOURCE". If omitted, the default is "INDV_CLK_SOURCE". When set to"INDV_CLK_SOURCE", all transmitters are clocked using their individual clock source. When set to "TX_CH0_CLK_SOURCE", all transmitters are clocked by a single transmitter clock source.
RX_USE_RISING_EDGE_TRIGGERED_PATTERN_ALIGN String No

Specifies whether the word aligner realigns continuously or only once per rising edge of the rx_enapatternalign signal. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE". When set to "TRUE", the word aligner aligns only once per rising edge of the rx_enapatternalign signal. When set to "FALSE", the word aligner realigns continuously when the rx_enapatternalign signal is high.
RX_ENABLE_TRUE_COMPLEMENT_MATCH_IN_WORD_ALIGN String No

Specifies whether the word aligner aligns to both true and complement versions of the programmed pattern, or to only the true versions. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE". When set to "TRUE", the word aligner aligns to both true and complement versions of the programmed pattern set by the value of the RX_ALIGN_PATTERN signal. When set to "FALSE", the word aligner aligns only to true versions of the programmed pattern set by the value of the RX_ALIGN_PATTERN signal.
RX_USE_ALIGN_STATE_MACHINE String No

Specifies whether the alignment state machine controls the word aligner. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE". When set to "TRUE", the alignment state machine controls the word aligner. When set to "FALSE", no state machines are used.

If the RX_BITSLIP_ENABLE parameter value is "TRUE", the rx_bitslip signal controls the word aligner. If the RX_BITSLIP_ENABLE parameter value is "FALSE", word aligner is controlled by the rx_enapatternalign signal.
RX_BITSLIP_ENABLE String No

Specifies whether the rx_bitslip signal controls the word aligner. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE". When set to "TRUE", the rx_bitslip signal controls the word aligner. When set to "FALSE", the word aligner is controlled by the alignment state machine or the rx_enapatternalign signal depending on the value of the value of the RX_USE_ALIGN_STATE_MACHINE parameter.
RX_ALIGN_PATTERN String No

Specifies the word alignment pattern. The size of the bit vectors is specified by the value of the RX_ALIGN_PATTERN_LENGTH parameter.
RX_ALIGN_PATTERN_LENGTH Integer No

Specifies the length of the word alignment pattern. Values are [7,10,16]. When the deserialization factor is 8, the pattern length value must be 16. If the deserialization factor is 10, the pattern length value can be either 7 or 10.
RX_ALIGN_LOSS_SYNC_ERROR_NUM Integer No

Determines the number of bad data words required for the alignment state machine in the word aligner to enter the loss of synch state, where the rx_syncstatus signal goes low. Values are [7..0].
RX_NUM_ALIGN_CONS_GOOD_DATA Integer No

Specifies the number of consecutive valid words needed to reduce the built-up error count by 1. Values are [256..1].
RX_NUM_ALIGN_CONS_PAT Integer No

Specifies the number of consecutive patterns needed to achieve synchronization. Values are [256..1].
RX_RUN_LENGTH Integer No

Specifies the maximum number of consecutive 1s or 0s allowed before a run length violation is reported through the RX_RLV signal.
RX_RUN_LENGTH_ENABLE String No

Flag that enables run length detection. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".

RX_8B_10B_MODE

 String No

Specifies the 8B/10B decoder/encoder mode for the receiver. Values are "NORMAL", "CASCADED", and "NONE". When set to "NONE", the 8B/10B encoder/decoder mode is bypassed. If omitted, the default is "NONE".
TX_8B_10B_MODE String No

Specifies the 8B/10B decoder/encoder mode for the transceiver. Values are "NORMAL", "CASCADED", and "NONE". When set to "NONE", the 8B/10B encoder/decoder mode is bypassed. If omitted, the default is "NONE".
TX_FORCE_DISPARITY_MODE String No

Specifies whether to enable disparity for the 8B/10B encoder based on the tx_forcedisp input signal value. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
TX_FORCE_KCHAR String No

Specifies whether the K character transmission is forced from the transmitter. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
TX_FORCE_ECHAR String No

Specifies whether the E character transmission is forced from the transmitter. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
TX_RXDETECT_CTRL String No

Specifies 2-bit control.
TX_LOW_SPEED_TEST_SELECT String No

Specifies 4-bit control.
TX_ALLOW_POLARITY_INVERSION String No

Specifies whether the polarity inversion is performed using the tx_invpolarity input signal. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
TX_ENABLE_SYMBOL_SWAP String No

Specifies whether the high and low bytes are swapped after 8B/10B encoding. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".

TX_PLL_INCLK0_PERIOD

 String No

Specifies the dedicated input clock period, in picoseconds (ps), for the atom inclock period.

TX_PLL_INCLK0_PERIOD

 String No

Specifies the dedicated input clock period, in picoseconds (ps), for the atom inclock period.
TX_PLL_VCO_MULTIPLY_BY Integer No Specifies the clock multiplication factor generated by the transmitter PLL.
TX_PLL_VCO_DIVIDE_BY Integer No Specifies the clock division factor generated by the transmitter PLL.
TX_PLL_MULTIPLY_BY String No Specifies the clock multiplication factor generated by the PLL.
TX_PLL_DIVIDE_BY String No Specifies the clock division factor generated by the PLL.
TX_ENABLE_BIT_REVERSAL String No

Specifies whether bit ordering output is reversed after 8B/10B encoding. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
TX_ENABLE_SELF_TEST_MODE String No

Specifies whether the self-test mode is enabled. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
TX_SELF_TEST_MODE String No

Specifies the self-test mode. Values are "PRBS_7", "PRBS_8", "PRBS_10", "PRBS_23", "LOW_FREQ", "MIXED_FREQ", "HIGH_FREQ", "INCREMENTAL", "CJPAT", and "CRPAT".
TX_FLIP_TX_IN String No

Specifies whether the transmitter input data bits are flipped. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
TX_USE_CORECLK String No

Specifies whether the tx_coreclk input port is used. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
VOD_CTRL_SETTING Integer No

Specifies the VOD switching control signal for various differential voltages. Values are [7..0].

PREEMPHASIS_CTRL_1STPOSTTAP_SETTING

 Integer No

Specifies the preemphasis control signal for the first post tap. Values are [15..0].

PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING

 Integer No

Specifies the preemphasis control signal for the second post tap. Values are [7..0].
PREEMPHASIS_CTRL_PRETAP_SETTING Integer No

Specifies the preemphasis control signal for the pretap. Values are [7..0].

PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING

 String No

Specifies whether the preemphasis control signal for the second post tap is inverted. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
PREEMPHASIS_CTRL_PRETAP_INV_SETTING String No

Specifies whether the preemphasis control signal for the pretap is inverted. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
TX_COMMON_MODE String No

Specifies the transmitter common mode voltage. Values are "TRISTATE", "0.6V", and "0.7V". If omitted, the default is "0.7V".
TX_ANALOG_POWER String No

Specifies the transmitter VCCHTX value. Values are "1.2V" and "1.5V". If omitted, the default is "1.5V".
TX_CHANNEL_BONDING String No

Specifies the protocol bonding type. Values are "INDV", "X4", and "X8". If omitted, the default is "INDV".
CMU_PLL_LOOP_FILTER_RESISTOR_CONTROL Integer No

Specifies the 2-bit setting for the PLL bandwidth. Values are [3..0].

RX_8B_10B_COMPATIBILITY_MODE

 String No

Specifies the 8B/10B encoder/decoder mode for the receiver. Values are "TRUE" (StratixGX-compatible mode) and "FALSE" (IBM-compatible mode). If omitted, the default is "FALSE".
TX_8B_10B_COMPATIBILITY_MODE String No

Specifies the 8B/10B encoder/decoder mode for the transmitter. Values are "TRUE" (StratixGX-compatible mode) and "FALSE" (IBM-compatible mode). If omitted, the default is "FALSE".
RX_RATE_MATCH_FIFO_MODE String No

Specifies the rate matching state machine mode. Values are "NORMAL", "CASCADED", and "NONE". If omitted, the default is "NONE". When set to "NORMAL", the rate matching state is single width internal datapath and rate matching state machine control. When set to "CASCADED", the rate matching state is double width internal datapath and rate matching state machine control. When set to "NONE", the rate matching FIFO is disabled.

RX_RATE_MATCH_PATTERN1

 String No

Specifies the rate matching pattern in 20-bit binary strings.

RX_RATE_MATCH_PATTERN2

 String No

Specifies the rate matching pattern in 20-bit binary strings. This parameter is available only when the RX_USE_RATE_MATCH_PATTERN1_ONLY parameter value is set to "FALSE".

RX_USE_RATE_MATCH_PATTERN1_ONLY

 String No

Specifies whether the word aligner aligns to the pattern programmed into the RX_RATE_MATCH_PATTERN1 parameter. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_RATE_MATCH_PATTERN_SIZE Integer No

Specifies the rate matching pattern size in the RX_RATE_MATCH_PATTERN1 and RX_RATE_MATCH_PATTERN2 parameters. Values are 10 and 20.
RX_RATE_MATCH_SKIP_SET_BASED String No

Specifies whether to skip set-based, as in PCI-Express. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_RATE_MATCH_BACK_TO_BACK String No

Specifies whether to allow insertion or deletion of consecutive characters or an ordered set. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_RATE_MATCH_ORDERED_SET_BASED String No

Specifies whether rate matching is ordered set-based equivalent to the PROTOCOL parameter set to GIGE. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_BYTE_ORDERING_MODE String No

Specifies the byte ordering mode. Values are "PATTERN-BASED", "SYNCSTATUS-BASED", and "NONE". If omitted, the default is "NONE". When set to "PATTERN-BASED", byte ordering is based on the programmed 10-bit pattern. When set to "SYNCSTATUS-BASED", byte ordering is based on the syncstatus signal from the word aligner. When set to "NONE", the byte ordering is disabled.
RX_BYTE_ORDER_PLD_CTRL_ENABLE String No

Specifies the byte order for the PLD. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_BYTE_ORDER_PATTERN String No

Specifies the byte ordering (SOP) pattern. Values are [10..8], and are dependent on the block data width. If the 8B10B is used, the pattern must be 9 bits wide with the control character at bit 8. If the 8B/10B encoder/decoder is not used and the deserialization is 10/20 bits wide, then the byte ordering pattern must be 10 bits wide. If the 8B10B is not used and the deserialization is 8/16 bits wide (SONET-style), then the byte ordering pattern must be 8 bits wide.
RX_BYTE_ORDER_PAD_PATTERN String No

Specifies the 10-bit pad pattern at the byte ordering block in 10-bit binary strings. If the deserailization factor is 8/16 bits wide, the byte ordering pad pattern is 8bits. If the 8B/10B encoder/decoder is used, 9bits and the control character should be set at bit 8.

If the 8B/10B encoder/decoder is not used and the deserialization factor is 10/20 bits wide, the byte ordering pad pattern is 10 bits.
RX_ALLOW_PIPE_POLARITY_INVERSION String No

Specifies whether to enable the polarity inversion at the input of the 8B/10B encoder/decoder based on the value of the pipe8b10binvpolarity input port. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_DISABLE_AUTO_IDLE_INSERTION String No

Specifies whether to disable the idle insertion in the phase compensation/interface FIFO. Values are "TRUE" and "FALSE". When set to "TRUE", the idle insertion is disabled, and when set to "FALSE", the idle insertion is enabled. If omitted, the default is "FALSE".
RX_ENABLE_SELF_TEST_MODE String No

Specifies whether to enable the self-test mode circuit. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_SELF_TEST_MODE String No

Specifies the self-test mode. Values are "PRBS_7", "PRBS_8", "PRBS_10", "PRBS_23", "LOW_FREQ", "MIXED_FREQ", "HIGH_FREQ", "INCREMENTAL", "CJPAT", and "CRPAT".
RX_FORCE_SIGNAL_DETECT String No

Specifies whether to force signal detection in the receiver's CRU. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_PPMSELECT Integer No

Specifies the parts per million (PPM) setting to measure the frequency difference between the input clocks. Values are [63..0].

PPMSEL[5:0]/ PPMSELECT

Effective PPM Setting

100000

1000PPM

010000

500PPM

001000

300PPM

001001

250PPM

000100

200PPM

000010

125PPM

000001

100PPM

000011

62.5PPM

111111

freqlock stays high

All other settings

freqlock stays low

RX_0PPM_CORE_CLOCK

 String No

Specifies the receiver 0 PPM clock source. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
TX_0PPM_CORE_CLOCK String No

Specifies the transceiver 0 PPM clock source. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_CRU_USE_REFCLK_PIN String No

Specifies that the inclk source of the PLL receiver comes from a refclk pin. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_CRU_REFCLK_MULTIPLY_BY String No

Specifies the multiplication factor for the CRU refclk pin. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE". This parameter is available only when the RX_CRU_USE_REFCLK_PIN parameter value is set to "TRUE".
RX_CRU_REFCLK_DIVIDE_BY String No

Specifies the divide factor for the refclk pin for the CRU. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE". This parameter is available only when the RX_CRU_USE_REFCLK_PIN parameter value is set to "TRUE".
RX_DATAPATH_LOW_LATENCY_MODE String No

Specifies whether the latency mode value for the datapath is set to low for the receiver. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
ELEC_IDLE_INFER_ENABLE String No

Specifies whether to enable the electrical idle inference selection block. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_CDRCTRL_ENABLE String No

Specifies whether to enable the CDR control block for the receiver. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_CRU_DATA_RATE Integer No

Specifies the output period in picoseconds (ps). Output frequency is data_rate / 2. If omitted, the default is 0.
RX_BANDWIDTH_MODE Integer No

Specifies the bandwidth setting for the receiver PLL. Values are [3..0].
RX_ENABLE_DC_COUPLING String No

Specifies whether to enable DC coupling to the receiver input pins. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_SIGNAL_DETECT_THRESHOLD Integer No

Specifies the signal detect and the signal loss thresholds for the receiver input buffer. Values are [7..0].
EQUALIZER_CTRL_A_SETTING Integer No

Specifies the equalizer control A setting. Values are [7..0].
EQUALIZER_CTRL_B_SETTING Integer No

Specifies the equalizer control B setting. Values are [7..0].
EQUALIZER_CTRL_C_SETTING Integer No

Specifies the equalizer control C setting. Values are [7..0].
EQUALIZER_CTRL_D_SETTING Integer No

Specifies the equalizer control D setting. Values are [7..0].
EQUALIZER_CTRL_V_SETTING Integer No

Specifies the equalizer control V setting. Values are [7..0].
RX_COMMON_MODE String No

Specifies the receiver common mode voltage. Values are "TRISTATE", "0.9V", and "1.2V".
RX_USE_CRUCLK String No

Specifies whether to use the rx_cruclk input port. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_USE_CLKOUT String No

Specifies whether to use the rx_clkout output port. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_USE_PIPE8B10BINVPOLARITY String No

Specifies whether the pipe8b10binvpolarity input port is connected. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_FLIP_RX_OUT String No

Specifies if the receiver output data bits are flipped. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_CHANNEL_BONDING String No

Specifies protocol bonding type. Values are "INDV", "X4", and, "X8". When set to "INDV", the protocol type is individual channel bonding. When set to "X4", the protocol uses 4 channel bonding. When set to "X8", the protocol uses 8 channel bonding.
ENABLE_PLL_INCLK_DRIVE_RX_CRU String No

Specifies whether the pll_inclk input port drives the receiver input clock. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE". When set to "TRUE", the pll_inclk input port drives the receiver"™s reference input clock. When set to "FALSE", the rx_cruclk input port drives the receiver"™s reference input clock. This parameter is applicable only when there is no CMU PLL reconfiguration.

ENABLE_PLL_INCLK0_DIVIDER

ENABLE_PLL_INCLK1_DIVIDER

ENABLE_PLL_INCLK2_DIVIDER

ENABLE_PLL_INCLK3_DIVIDER

ENABLE_PLL_INCLK4_DIVIDER

ENABLE_PLL_INCLK5_DIVIDER

ENABLE_PLL_INCLK6_DIVIDER

 String No

Specifies whether the refclk divider is used for the inclk[]. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
USE_CALIBRATION_BLOCK String No

Specifies whether the calibration block is instantiated in the Intel® FPGA IP. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_USE_DESKEW_FIFO String No

Specifies whether to enable the deskew FIFO. This parameter can also be enabled for non-XAUI configurations. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_ELEC_IDLE_K_DETECT String No

Specifies whether to enable K28.7 detection for electrical idle exit detection. Values are "TRUE" and "FALSE". A value of "FALSE" is unavailable to the PMA module.
RX_ELEC_IDLE_NUM_COM_DETECT Integer No

Specifies the number of commas required to enter or exit electrical idle. Values are [3..1]. If the value is greater than 2, the syncstatus output port is used.
RX_CRU_MULTIPLICATION_VALUE Integer No Specifies the clock multiplication factor generated by the receiver PLL.
RX_CRU_MULTIPLY_BY Integer No Specifies the clock multiplication factor generated by the receiver PLL.
RX_CRU_PFD_CLK_SELECT Integer No Specifies the active input clock index.
RX_CRU_DIVIDE_BY Integer No Specifies the clock division factor generated by the receiver PLL.
RX_NUM_ALIGN_CODE_GROUPS_IN_ORDERED_SET Integer No

Specifies the number of code groups in an ordered set for word aligner to consider. Values are [3..0].
RX_ALLOW_ALIGN_POLARITY_INVERSION String No

Specifies polarity inversion of data output based on the rx_invpolarity input signal.

Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_ENABLE_BIT_REVERSAL String No

Specifies whether to use reverse bit ordering by the word aligner for data output based on the rx_revbitorderwa input signal. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_ENABLE_DEEP_ALIGN_BYTE_SWAP String No

Specifies whether to use byte swapping in deep word alignment based on the rx_revbitorderwa input signal. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_DESKEW_PATTERN Integer No

Specifies the deskew pattern as a 10-bit integer string. This value is set when the RX_CUSTOM_DESKEW_PATTERN parameter is enabled. If omitted, the default is set to the value of the XAUI deskew pattern.
RX_CUSTOM_DESKEW_PATTERN String No

Specifies whether to enable the custom deskew pattern based on the value of the RX_DESKEW_PATTERN parameter. This parameter can also be enabled for non-XAUI configurations. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
RX_FORCE_FREQ_DET_LOW String No

Specifies whether to force frequency detection to low. Values are "TRUE" and "FALSE".
RX_FORCE_FREQ_DET_HIGH String No

Specifies whether to force frequency detection to high. Values are "TRUE" and "FALSE".
RX_DISABLE_RUNNING_DISP_IN_WORD_ALIGNER String No

Specifies whether to run disparity computation in the word aligner. Values are "TRUE" and "FALSE". When set to "TRUE", the RX_DISABLE_RUNNING_DISP_IN_WORD_ALIGNER parameter is disabled. If omitted, the default is "TRUE".
RX_RATE_MATCH_ALMOST_EMPTY_THRESHOLD Integer No

Specifies the limit at which the rate matching FIFO is considered almost empty. Values are [15..0].
RX_RATE_MATCH_ALMOST_FULL_THRESHOLD Integer No

Specifies the limit at which the rate matching FIFO is considered almost full. Values are [15..0].
RX_ADAPTIVE_EQUALIZATION_MODE String No

Specifies the adaptive equalization engine mode. Values are "CONTINUOUS", "STOPPED", and "NONE". When set to "CONTINUOUS", the adaptive equalization engine is enabled and in continuous equalization mode. When set to "STOPPED", the adaptive equalization engine is enabled and in stopped mode.

When set to "NONE", the adaptive equalization engine is disabled.
RX_IGNORE_LOCK_DETECT String No

Specifies whether to ignore lock detection. Values are "TRUE" and "FALSE". When set to "TRUE", lock detection is ignored. When set to "FALSE", lock detection is observed.
RX_ENABLE_LOCK_TO_REFCLK_SIG String No

Specifies whether the CRU locks to the local refclk input based on the rx_locktorefclk input port value. Values are "TRUE" and "FALSE".
RX_ENABLE_LOCK_TO_DATA_SIG String No

Specifies whether the CRU locks to the data input based on the rx_locktodata input port value. Values are "TRUE" and "FALSE".
RX_INFINIBAND_INVALID_CODE String No

Specifies the invalid code setting for infiniband. Values are [3..0].
RX_FORCE_SIGNAL_DETECT_DIG String No

Specifies whether word aligner forces signal detection. Values are "TRUE" and "FALSE".
RX_INSERT_PAD_ON_UNDERFLOW String No

Specifies whether to insert a pad is on underflow. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
EQUALIZER_DCGAIN_SETTING Integer No

Specifies the equalizer gain. Values are [0,3,6,9,12]. Section values are as follows: 0:0db

3:3db

6 : 6 db

9 : 9 db

12 : 12 db
RX_USE_CORECLK String No

Specifies whether to use the rx_coreclk input port. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
CMU_OFFSET_ALL_ERRORS_ALIGN String No

Specifies whether to align offset errors in the central management unit (CMU). Values are "TRUE" and "FALSE".
USE_GLOBAL_CLK_DIVIDER String No

Specifies whether the CMU clock divider is used. Values are "TRUE", "FALSE", and "AUTO". If omitted, the default is "AUTO". If the design is quad bonded and the value is set to "AUTO", CMU clock divider use is enabled.

ENABLE_0PPM

 String No Enables the PCIE low latency mode.
TX_PLL_PFD_CLK_SELECT Integer Yes

Specifies the active inclk index. Values are [9..0]. If omitted, the default is 0.
TX_PLL_USE_REFCLK_PIN String No

Specifies whether the inclk source of the PLL transceiver comes from a refclk pin. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
TX_PLL_REFCLK_MULTIPLY_BY Integer No

Specifies the refclk pin multiplication factor. If omitted, the default is 0. This parameter is available only when the TX_PLL_USE_REFCLK_PIN parameter value is set to "TRUE".
TX_PLL_REFCLK_DIVIDE_BY Integer No

Specifies the divide factor for the refclk pin for the PLL. If omitted, the default is 0. This parameter is available only when the TX_PLL_USE_REFCLK_PIN parameter value is set to "TRUE".
TX_DATAPATH_LOW_LATENCY_MODE String No

Specifies whether the latency mode value for the datapath is set to low for the transceiver. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
TX_PLL_VCO_DATA_RATE Integer No

Specifies the VCO base output period in picoseconds (ps). Output frequency is data_rate / 2. If omitted, the default is 0.
TX_PLL_DATA_RATE Integer No

Specifies the output period in picoseconds (ps). Output frequency is data_rate / 2. If omitted, the default is 0.
gen_reconfig_pll String No

Specifies whether to generate a secondary PLL for the reconfiguration. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE". Applicable when reconfiguration is turned on.
tx_use_serializer_double_data_mode String No

Specifies the bit width from the interface to the serializer. Values are "TRUE" and "FALSE". If "TRUE", the interface to the serializer is 16/20 bits wide, if "FALSE" the interface to the serializer is 8/10 bits wide. If omitted, the default is "FALSE".
cmu_pll_log_index Integer No

Specifies the logical index for primary PLL. Integer value 0 and 1. Applicable only when gen_reconfig_pll is set to "TRUE". The default is 0.
cmu_pll_reconfig_log_index Integer No

Specifies the logical index for secondary PLL. Integer value 0 and 1. Applicable only when gen_reconfig_pll is set to "TRUE". The default is 0.
cmu_pll_inclk_log_index Integer No

Specifies which input clock source is selected by the primary CMU PLL. Integer value from 0 until 6. The default is 0.
cmu_pll_reconfig_inclk_log_index Integer No

Specifies which input clock source is selected by the secondary CMU PLL. Integer value from 0 until 6. The default is 0.
enable_reconfig_pll_inclk_drive_rx String No

Specifies whether the CRU is driven by the same input clock source of the CMU PLL. Values are "TRUE" and "FALSE". If omitted, the default is "TRUE". Applicable only when reconfig_dprio_mode is set to CMU PLL reconfiguration.
reconfig_pll_inclk_width Integer No

Specifies the width of the reconfig_pll_inclk input port, which is used when the reconfig_dprio_mode parameter is set to enable CMU PLL reconfiguration.
reconfig_calibration String No

Specifies whether RX calibration is enabled. Values are "TRUE" and "FALSE". If "TRUE", RX calibration is enabled. If omitted, the default is "FALSE".
enable_pma_direct String No

Specifies whether PMA-direct mode is enabled. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
enable_pma_xn_bonding String No

Specifies whether to enable xN bonding for PMA-direct mode. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
enable_lc_tx_pll String No

Specifies whether to enable the ATX PLL. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
tx_phfiforegmode String No

Specifies whether to enable TX PCS ph_fifo_reg_mode WYSIWYG parameter. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
tx_bitslip_enable String No

Specifies whether to enable the bit slip feature for all modes. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".
pll_pfd_fb_mode String No

Specifies the source of the PFD feedback clock on the TX PLL. Values are "internal", "iqtxrxclk", "pldclk". If omitted, the default is "internal".
advanced_calibration_clocking String No

Specifies whether to expose fixedclk port for RX calibration. Values are "TRUE" and "FALSE". If omitted, the default is "FALSE".