Clear box example

To generate a single-clock FIFO for Stratix® devices with 256 words of 16-bit data, the clear box command-line tool would be used with the following arguments:

clearbox cbx_scfifo.dll DEVICE_FAMILY=Stratix® lpm_numwords=256 lpm_width=16 CBX_FILE=my256x16fifo.v
  • Clear box generator DLLs may not support all the combinations of parameters and ports that are supported by the corresponding Intel® FPGA IP. For example, most clear box generator DLLs do not support older device families.
  • The Verilog or VHDL output of a clear box Intel® FPGA IP generator may be used with third-party EDA synthesis tools to improve timing-driven synthesis. Contact the vendor to verify clear box Intel® FPGA IP support.