ModelSim® Gate-Level Functional Simulation Example for VHDL

The following example shows a typical gate-level functional simulation in the ModelSim® software for VHDL. You can create a script that performs the following steps:

  • Compiles the altera_mf.vhd, 220model.vhd, 220pack.vhd libraries.
  • Compiles the VHDL Design File (.vhd) Definition generated by the IP Catalog with the ModelSim® software. In this example, the file is my_pll.vhd.
  • Compiles the top-level VHDL Design File with the ModelSim® software. In this example, the file name is pll_design.vhd.
  • Compiles the testbench file. In this example, the testbench file name is plltest.vhd.

Timing simulation for Stratix® V devices is not supported in the Intel® Quartus® Prime 10.1 release.

You can simulate this sample design in the ModelSim® software by using the commands shown in the following sample script:

            vlib work                                       # Create working directory
vcom /quartus/eda/sim_lib/altera_mf.vhd         # Compile the altera_mf library
vcom /quartus/eda/sim_lib/altera_mf_components.vhd         # Compile the altera_mf_components library
exec vmap altera_mf work                        # Create altera_mf library and map it to work
vcom my_pll.vhd                                 # Compile generated Intel® FPGA IP file
vcom pll_design.vhd                             # Compile source instantiating module
vcom plltest.vhd                                # Compile the testbench file
vsim -t ps work.plltest(behave)                 # Simulate plltest with resolution in ps
add wave /plltest/*                             # Add the port signals to the waveform view
add wave /plltest/U0/U0/clock1                  # Add the clock1 altclklock signal to the 
                                                # waveform view
run 1000 ns                                     # Run the simulation for 1000 ns