Setting Up Device-Wide Signals in Verilog HDL for Questa® - Intel® FPGA Edition

To set up a Verilog Output File (.vo) Definition that contains device-wide reset or device power up signals, add the following code to your testbench file before starting simulation:
reg  <device-wide reset>;
reg  <device power up>;  
<device power up> = 0;    
#<time> <device power up> = 1; 
Note: The variable <device-wide reset> is the name of the device-wide reset signal, <device power up> is the name of the device power up signal, and <time> is a time value between 0 and the actual starting time of the simulation.