RES-30007: External Reset Signals Not Synchronized Using Two Cascaded Registers

In a design, an asynchronous external reset can affect the recovery time of a register, cause stability problems, and reset state machines to incorrect states. You must synchronize an external reset, which is a primary input that is used as a reset signal, using two cascaded registers triggered on the same edge.

The following image shows an example of an asynchronous external reset that is not synchronized:

Figure 1. External Reset That is not Synchronized


Follow these guidelines for the synchronized external reset:

  • Synchronize the external reset with two cascading registers.
  • Trigger the cascading registers on the same clock edge.

The following image shows an example of a correctly synchronized external reset:

Figure 2. Correctly Synchronized External Reset

Asynchronous resets are permitted in circumstances where the reset can be released synchronously, most often through the use of a synchronizer circuit. For example, if your design feeds the reset signal from the cascaded register on the active low CLR port, the D-port of the first cascaded synchronizing register must feed the VCC port. Cascaded registers and reset registers that are fed from the second register in the cascade should all have the same clock source.

The following image is an example of an asynchronous synchronizing reset:

Figure 3. Asynchronous Synchronizing Reset




Analysis and Elaboration

Device Family

  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10