WIRE (Block Design Files only) Primitive
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Name: |
Output Description: |
Input Description: |
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WIRE |
OUT = input |
IN |
The WIRE primitive is used to rename a node or bus line. WIRE primitives do not have any associated logic behavior.
The WIRE primitive is directional; that is, on a bidirectional bus, you can use only one WIRE primitive to rename the input or output portion of the bus.
Note: In Verilog HDL, the buf gate primitive has the same functionality as
the WIRE primitive. For information about Quartus® Prime primitive
instantiation, go to Using a Quartus® Prime Logic Function.