Generating an IBIS Output File

You can generate an IBIS Output File (.ibs) Definition in the Quartus® Prime software to perform board-level signal integrity verification in other EDA tools.
Table 1. IBIS Model Access and Customization
IBIS Model Access and Customization Method

Stratix® 10 Devices

Arria® 10 Devices

Cyclone® 10 GX Devices

 Agilex™ FPGA Portfolio Devices
Obtaining IBIS Models
  • Download generic device family IBIS models from the Intel website to perform early simulations of the I/O buffers you expect to use in your design as part of a pre-layout analysis at: IBIS Models for Intel FPGA Devices. The downloaded models have the RLC package values set to one particular device in each device family.

    Or

  • Use the Quartus® Prime EDA Netlist Writer GUI to generate custom IBIS models that accurately reflect your device and assignments.
  • Quartus® Prime Pro Edition installation includes the IBIS models and IBIS Writer script for Agilex™ FPGA portfolio devices in: /common/misc/ibis_writer/

    Or

  • Download generic device family IBIS models from the Intel website to perform early simulations of the I/O buffers you expect to use in your design as part of a pre-layout analysis at: IBIS Models for Intel FPGA Devices. The downloaded models have the RLC package values set to one particular device in each device family and require customization for accurate simulation.
Customizing IBIS Models
  • For more accurate IBIS module simulation, you must first customize any generic IBIS files that you download from the Intel website with the correct RLC values for the specific device package you have selected for your design.

    Or

  • Generate custom IBIS files that with Intel Quartus Prime EDA Netlist Writer. IBIS files that you generate with the EDA Netlist Writer automatically include the RLC values for your current target device.
Note: The ibis_writer.py script does not support generation of IBIS model files for Stratix® 10 devices, Arria® 10 devices, or Cyclone® 10 GX devices.
  • For more accurate IBIS module simulation, you must first customize the installed or downloaded IBIS model files with the correct RLC values for the specific target device package using the IBIS Writer script in /quartus/common/misc/ibis_writer/. The README.txt file in this directory provides complete instructions for using the script.
  • Alternatively, you can generate custom IBIS files by using the Quartus® Prime software EDA Netlist Writer GUI. IBIS files that you generate with the EDA Netlist Writer automatically include the RLC values for your current target device.
You can use the Quartus® Prime EDA Netlist Writer GUI to generate custom IBIS models.

IBIS files that you generate with the EDA Netlist Writer automatically include the RLC values for your current target device.

Before generating the custom IBIS model, you can specify I/O constraints to define things like drive strength, enabling of clamping diodes for ESD protection, and other settings. The custom IBIS models that EDA Netlist Writer generates then reflect the I/O assignments.

To generate custom IBIS models with the EDA Netlist Writer GUI, follow these steps:

  1. To specify the format, version, and output location of the generated model files, click Assignments > Settings > EDA Tool Settings.
  2. Under Board Level signal integrity analysis, specify IBIS for the Format, the supported IBIS version that you want, and the location of the Output directory for the generated files.
  3. Click Assignments > Device In the Device dialog box, click the Device and Pin Options button and review and specify any optional IBIS settings.
  4. To run the EDA Netlist Writer to generate the custom IBIS model files, click Processing > Start > Start EDA Netlist Writer.