TMC-20214: Buses with Incoming Paths Failing Setup Analysis with Multiple Sequential Adder Chains

Description

Violations of this rule indicate buses that are endpoints of setup-failing timing paths that contain multiple back-to-back adder chains.

Adder chains result in large segments of delay that the Compiler cannot optimize. Minimize the number of independent adder chains on a particular timing path by registering the output of each chain.

Parameters

Name Description Type Default Value Min Value Max Value
maximum_setup_slack Reports a violation for timing paths that have a setup slack below the value of this parameter. double 0.0    
to_clock_filter Reports a violation for timing paths that end at a register in a clock domain that matches the value of this parameter. string *    
minimum_number_of_adders Reports a violation for timing endpoints that are preceded by a number of independent adder chains greater than or equal to this value. integer 3    
minimum_number_of_soft_mult_chains Reports a violation for timing endpoints that are preceded by a number of independent adder chains that are implementing multiplier logic greater than or equal to this value. integer 2    

Recommendation

Add one or more pipeline register stages between the adder chains.

Severity

Medium

Tags

Tag Description
logic-levels Design rule checks which flag potentially problematic amounts of logic on a timing path.

Device Family

  • Intel®Stratix® 10
  • Intel Agilex®
  • Intel®Arria® 10
  • Intel®Cyclone® 10 GX