set_input_delay (::quartus::sdc)

The following table displays information for the set_input_delay Tcl command:

Tcl Package and Version

Belongs to ::quartus::sdc 1.5

Syntax set_input_delay [-h | -help] [-long_help] [-add_delay] [-blackbox] -clock <name> [-clock_fall] [-fall] [-max] [-min] [-reference_pin <name> ] [-rise] [-source_latency_included] <delay> <targets>
Arguments -h | -help Short help
-long_help Long help with examples and possible return values
-add_delay Create additional delay constraint instead of overriding previous constraints
-blackbox Create an assignment for a partition boundary port causing it to be treated as a port
-clock <name> Clock name
-clock_fall Specifies that input delay is relative to the falling edge of the clock
-fall Specifies the falling input delay at the port
-max Applies value as maximum data arrival time
-min Applies value as minimum data arrival time
-reference_pin <name> Specifies a pin or port in the design to which the input delay is relative
-rise Specifies the rising input delay at the port
-source_latency_included Specifies that input delay includes added source latency
<delay> Time value
<targets> List of input port type objects
Specifies the data arrival times at the specified input ports relative
the clock specified by the -clock option. The clock must refer to a
clock name in the design.

Input delays can be specified relative to the rising edge (default) or
falling edge (-clock_fall) of the clock.

Input delays can be specified relative to a pin or a port (-reference_pin)
in the clock network. Clock arrival times to the reference pin or port
are added to data arrival times.

        If no -reference_pin is specified, if the input delay is specified
        relative to a generated clock with a single target, the clock arrival
        times to the generated clock are added to the data arrival time. If the
generated clock has multiple targets, the worst case arrival time to
those targets will be used.

Input delays can already include clock source latency. By default the
clock source latency of the related clock is added to the input delay
value, but when the -source_latency_included option is specified, the
clock source latency is not added because it was factored into the
input delay value.

The maximum input delay (-max) is used for clock setup checks or
recovery checks and the minimum input delay (-min) is used for clock
hold checks or removal checks. If only -min or -max (or neither) is
specified for a given port, the same value is used for both.

Separate rising (-rise) and falling (-fall) arrival times at the port
can be specified. If only one of -rise and -fall are specified for a
given port, the same value is used for both.

By default, set_input_delay removes any other input delays to the port
except for those with the same -clock, -clock_fall, and -reference_pin
combination. Multiple input delays relative to different clocks, clock
edges, or reference pins can be specified using the -add_delay option.

The value of the targets is either a collection or a Tcl list of
wildcards used to create a collection of the appropriate type.  The
values used must follow standard Tcl or Timing Analyzer-extension
substitution rules. See help for the use_timing_analyzer_style_escaping
command for details.  
Example Usage
# Simple input delay with the same value for min/max and rise/fall:
# 1) set on ports with names of the form myin*
set_input_delay -clock clk 1.5 [get_ports myin*]
# 2) set on all input ports
set_input_delay -clock clk 1.5 [all_inputs]

# Input delay with respect to the falling edge of clock
set_input_delay -clock clk -clock_fall 1.5 [get_ports myin*]

# Input delays for different min/max and rise/fall combinations
set_input_delay -clock clk -max -rise 1.4 [get_ports myin*]
set_input_delay -clock clk -max -fall 1.5 [get_ports myin*]
set_input_delay -clock clk -min -rise 0.7 [get_ports myin*]
set_input_delay -clock clk -min -fall 0.8 [get_ports myin*]

# Adding multiple input delays with respect to more than one clock
set_input_delay -clock clkA -min 1.2 [get_ports myin*]
set_input_delay -clock clkA -max 1.8 [get_ports myin*]
set_input_delay -clock clkA -clock_fall 1.6 [get_ports myin*] -add_delay
set_input_delay -clock clkB -min 2.1 [get_ports myin*] -add_delay
set_input_delay -clock clkB -max 2.5 [get_ports myin*] -add_delay

# Specifying an input delay relative to an external clock output port
set_input_delay -clock clk -reference_pin [get_ports clkout] 0.8 [get_ports myin*]

# Specifying an input delay relative to the clock pin of a register
set_input_delay -clock clk -reference_pin [get_pins regA|clk] 0.8 [get_ports myin*]
Return Value Code Name Code String Return
TCL_OK 0 INFO: Operation successful
TCL_ERROR 1 ERROR: Incorrect collection type. Expected a collection of type <string>.
TCL_ERROR 1 ERROR: Options -<string> and -<string> are mutually exclusive. Specify only one of the two options.
TCL_ERROR 1 ERROR: Timing netlist does not exist. Use create_timing_netlist to create a timing netlist.