remove_clock_latency (::quartus::sdc)

The following table displays information for the remove_clock_latency Tcl command:

Tcl Package and Version

Belongs to ::quartus::sdc 1.5

Syntax remove_clock_latency [-h | -help] [-long_help] -source <targets>
Arguments -h | -help Short help
-long_help Long help with examples and possible return values
-source Specifies the source clock latency
<targets> Valid destinations (string patterns are matched using Tcl string matching)
Removes clock latency for a given clock or clock target.

There are two types of latency: network and source.  Network latency
is the clock network delay between the clock and register clock pins.
Source latency is the clock network delay between the clock and its
source (e.g., a system clock or a base clock of a generated clock).

The Timing Analyzer automatically computes network latencies
for all register and generated clocks. Overriding clock network
latencies is not supported by the Timing Analyzer. Therefore, the
-source option must always be specified. Remove_clock_latency requires
this option as well.

You can apply clock latency to a clock, which affects all targets of
the clock, or to a specific clock target. Therefore, you can remove
clock latency from a collection of clocks, or from a collection of
target nodes. remove_clock_latency removes all latencies from a clock
or node, so removing a node's clock latency with respect to a
particular clock, or removing only latencies with particular
conditions is not supported.

The value of the targets is either a collection or a Tcl list of
wildcards used to create a collection of the appropriate type.  The
values used must follow standard Tcl or Timing Analyzer-extension
substitution rules.  See the help for use_timing_analyzer_style_escaping for
Example Usage
create_clock -name SYSCLK -period 10.000 [get_ports inclk]
create_generated_clock -name OUTCLK -divide_by 1 -source [get_ports inclk] [get_ports outclk]
create_generated_clock -name FDBKCLK -divide_by 1 -source [get_ports outclk] [get_ports fdbkclk]

# Apply a simple 2.000 ns source latency to the system clock.
set_clock_latency -source 2.000 [get_clocks SYSCLK]

# Specify feedback clock latencies between output port outclk
# and the output port fdbkclk.
set_clock_latency -source -late -rise 0.800 [get_clocks FDBKCLK]
set_clock_latency -source -late -fall 0.750 [get_clocks FDBKCLK]
set_clock_latency -source -early -rise 0.500 [get_clocks FDBKCLK]
set_clock_latency -source -early -fall 0.460 [get_clocks FDBKCLK]

# Remove all clock latency from FDBKCLK
remove_clock_latency -source [get_clocks FDBKCLK]
Return Value Code Name Code String Return
TCL_OK 0 INFO: Operation successful
TCL_ERROR 1 ERROR: Timing netlist does not exist. Use create_timing_netlist to create a timing netlist.