enhanced PLL Definition

A feature available in Stratix^® IV devices that employ a phase-locked loop (PLL). The enhanced PLL provides dynamic and manual clock switchover, programmable duty cycle, PLL reconfiguration, programmable phase shift, and programmable delay.

In Stratix^® IV family devices, the enhanced PLL is referred to as the top/bottom PLL.

You can take advantage of the enhanced PLL with the altpll Intel^® FPGA IP.